chipsalliance / chipsalliance/rocket-chip
sc.w was executed incorrectly in Rocket
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- Scala
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Description
**Type of issue**: bug report
**Impact**: unknown
**Development Phase**: proposal
**Other information**
Hello, when using the Rocket core, the `sc.w`, which should have failed, was executed by Rocket. For example, the following instruction:
```assembly
l0: la x15, data
addi x15, x15, 0
lr.d x12, (x15)
l1: la x23, data
addi x23, x23, 12
sc.w x14, x8, (x23)
...
data: .dword 0x25b0b9a021799aeb, 0x24db3c5f591237f4
...
```
The `lr.d` instruction was not set at location `(x23)`, so the `sc.w` operation should have failed. However, when we executed the above instruction using the Spike and Rocket core separately, we observed different results. In Spike, the register `x14` (which records whether `sc.w` executed successfully, with an initial value of a random number other than 0 or 1) was set to a non-zero value, `0x0000000000000001`, indicating that `sc.w` failed in Spike. But in Rocket, it was set to zero, `0x0000000000000000`, indicating that `sc.w` succeeded in Rocket, and the data was successfully stored at the corresponding location.
Can you tell me why Rocket handles such examples this way?
Thanks!
Contributor guide
Research direction
Reproduce the provided assembly sequence with the Rocket core and Spike, focusing on the lr.d at (x15) followed by sc.w at (x23). Compare x14 and the target data after execution, then document why Rocket and Spike produce different results and what behavior is correct.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 30/100