chipsalliance / chipsalliance/rocket-chip
A RV64 with usingVM=false config will throw firrtl exception
- Dominant language
- Scala
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Description
It's true that this is an unsual config, but maybe it's worth initiating an issue, I setup a RV64 with usingVM being false, and the firrtl lowering will complain about the following:
`PTW.scala:298: High index 26 is out of range [0, 20] in class freechips.rocketchip.rocket.PT`
The loc in line 298 of PTW.scala is :
`val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits)`
the r_req.addr is `vpnBits` width, and it's `(paddrBits + 1) min xLen` when usingVM is false, but the up index `maxSVAddrBits-pgIdxBits-1` seems always expect the usingVM is true. Therefore there is an out-of-range exception.
I don't know if it's worth fixing, but just post here so that others can be aware of this.
Thanks for your work.
Contributor guide
Research direction
Start at PTW.scala:298 and inspect how r_req.addr width and maxSVAddrBits are derived when usingVM=false. Reproduce the FIRRTL lowering failure with an RV64 configuration using that setting, then confirm that lowering completes without the reported out-of-range exception.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- compilers
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 42/100