How to make TraceGen configurations and scripts work?

**Type of issue**: bug report

**Impact**: unknown

**Development Phase**: request

**Other information**

I want to generate mem tarce using the script `tracegen.py`. But I can't make the emulator with CONFIG=TraceGenConfig successfully. How to make these configurations and scripts work again?

https://github.com/chipsalliance/rocket-chip/blob/master/scripts/tracegen.py
> This script generates a trace using the given emulator (built
> with CONFIG=TraceGenConfig). It waits until all cores have
> completed trace generation before terminating the emulator.

make and error log:
```
➜ emulator git:(master) ✗ make CONFIG=freechips.rocketchip.groundtest.TraceGenConfig
mkdir -p /home/hengyu/zspace/cpu/rocket-chip/emulator/generated-src/
cd /home/hengyu/zspace/cpu/rocket-chip && java -Xmx2G -Xss8M -cp /home/hengyu/zspace/cpu/rocket-chip/rocketchip.jar freechips.rocketchip.system.Generator -td /home/hengyu/zspace/cpu/rocket-chip/emulator/generated-src -T freechips.rocketchip.system.TestHarness -C freechips.rocketchip.groundtest.TraceGenConfig
Exception in thread "main" java.lang.reflect.InvocationTargetException
at ... ()
at freechips.rocketchip.stage.phases.PreElaboration.$anonfun$transform$1(PreElaboration.scala:36)
at ... ()
at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)
Caused by: java.lang.IllegalArgumentException: requirement failed: Key TLNetworkTopologyLocated(Location(InSubsystem)) is not defined in Parameters
at scala.Predef$.require(Predef.scala:337)
at org.chipsalliance.cde.config$View.apply(config.scala:29)
at freechips.rocketchip.subsystem.HasConfigurableTLNetworkTopology.$init$(BaseSubsystem.scala:62)
at freechips.rocketchip.subsystem.BaseSubsystem.(BaseSubsystem.scala:73)
at freechips.rocketchip.subsystem.RocketSubsystem.(RocketSubsystem.scala:33)
at freechips.rocketchip.system.ExampleRocketSystem.(ExampleRocketSystem.scala:11)
at freechips.rocketchip.system.TestHarness.(TestHarness.scala:16)
at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
at freechips.rocketchip.stage.phases.PreElaboration.$anonfun$transform$1(PreElaboration.scala:36)
at chisel3.Module$.do_apply(Module.scala:53)
at chisel3.stage.phases.Elaborate.$anonfun$transform$2(Elaborate.scala:40)
at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:884)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
at chisel3.internal.Builder$.build(Builder.scala:879)
at chisel3.stage.phases.Elaborate.$anonfun$transform$1(Elaborate.scala:40)
at scala.collection.immutable.List.flatMap(List.scala:293)
at scala.collection.immutable.List.flatMap(List.scala:79)
at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:28)
at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:21)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
at firrtl.options.Translator.transform(Phase.scala:248)
at firrtl.options.Translator.transform$(Phase.scala:248)
at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
at firrtl.Utils$.time(Utils.scala:181)
at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183)
at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179)
at scala.collection.immutable.List.foldLeft(List.scala:79)
at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
at chisel3.stage.ChiselStage.run(ChiselStage.scala:45)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
at firrtl.options.Translator.transform(Phase.scala:248)
at firrtl.options.Translator.transform$(Phase.scala:248)
at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183)
at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179)
at scala.collection.immutable.List.foldLeft(List.scala:79)
at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
at logger.Logger$.makeScope(Logger.scala:135)
at firrtl.options.Stage.transform(Stage.scala:47)
at firrtl.options.Stage.transform(Stage.scala:17)
at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
at firrtl.Utils$.time(Utils.scala:181)
at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183)
at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179)
at scala.collection.immutable.List.foldLeft(List.scala:79)
at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
at freechips.rocketchip.system.RocketChipStage.run(RocketChipStageGenerator.scala:44)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
at firrtl.options.Translator.transform(Phase.scala:248)
at firrtl.options.Translator.transform$(Phase.scala:248)
at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183)
at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179)
at scala.collection.immutable.List.foldLeft(List.scala:79)
at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
at logger.Logger$.makeScope(Logger.scala:135)
at firrtl.options.Stage.transform(Stage.scala:47)
at firrtl.options.Stage.execute(Stage.scala:58)
at firrtl.options.StageMain.main(Stage.scala:71)
at freechips.rocketchip.system.Generator.main(RocketChipStageGenerator.scala)
make: *** [Makefrag-verilator:13: /home/hengyu/zspace/cpu/rocket-chip/emulator/generated-src/freechips.rocketchip.system.TraceGenConfig.fir] Error 1
```
```
➜ emulator git:(master) ✗ make CONFIG=freechips.rocketchip.groundtest.TraceGenConfig MODEL=TestHarness PROJECT=freechips.rocketchip.groundtest
mkdir -p /home/hengyu/zspace/cpu/rocket-chip/emulator/generated-src/
cd /home/hengyu/zspace/cpu/rocket-chip && java -Xmx2G -Xss8M -cp /home/hengyu/zspace/cpu/rocket-chip/rocketchip.jar freechips.rocketchip.groundtest.Generator -td /home/hengyu/zspace/cpu/rocket-chip/emulator/generated-src -T freechips.rocketchip.groundtest.TestHarness -C freechips.rocketchip.groundtest.TraceGenConfig
Exception in thread "main" java.lang.reflect.InvocationTargetException
at ... ()
at freechips.rocketchip.stage.phases.PreElaboration.$anonfun$transform$1(PreElaboration.scala:36)
at ... ()
at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)
Caused by: java.lang.IllegalArgumentException: requirement failed: Key TLNetworkTopologyLocated(Location(InSubsystem)) is not defined in Parameters
at scala.Predef$.require(Predef.scala:337)
at org.chipsalliance.cde.config$View.apply(config.scala:29)
at freechips.rocketchip.subsystem.HasConfigurableTLNetworkTopology.$init$(BaseSubsystem.scala:62)
at freechips.rocketchip.subsystem.BaseSubsystem.(BaseSubsystem.scala:73)
at freechips.rocketchip.groundtest.GroundTestSubsystem.(GroundTestSubsystem.scala:14)
at freechips.rocketchip.groundtest.TestHarness.(TestHarness.scala:12)
at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
at freechips.rocketchip.stage.phases.PreElaboration.$anonfun$transform$1(PreElaboration.scala:36)
at chisel3.Module$.do_apply(Module.scala:53)
at chisel3.stage.phases.Elaborate.$anonfun$transform$2(Elaborate.scala:40)
at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:884)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
at chisel3.internal.Builder$.build(Builder.scala:879)
at chisel3.stage.phases.Elaborate.$anonfun$transform$1(Elaborate.scala:40)
at scala.collection.immutable.List.flatMap(List.scala:293)
at scala.collection.immutable.List.flatMap(List.scala:79)
at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:28)
at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:21)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
at firrtl.options.Translator.transform(Phase.scala:248)
at firrtl.options.Translator.transform$(Phase.scala:248)
at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
at firrtl.Utils$.time(Utils.scala:181)
at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183)
at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179)
at scala.collection.immutable.List.foldLeft(List.scala:79)
at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255) at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
at chisel3.stage.ChiselStage.run(ChiselStage.scala:45)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
at firrtl.options.Translator.transform(Phase.scala:248)
at firrtl.options.Translator.transform$(Phase.scala:248)
at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183)
at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179)
at scala.collection.immutable.List.foldLeft(List.scala:79)
at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
at logger.Logger$.makeScope(Logger.scala:135)
at firrtl.options.Stage.transform(Stage.scala:47)
at firrtl.options.Stage.transform(Stage.scala:17)
at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
at firrtl.Utils$.time(Utils.scala:181)
at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183)
at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179)
at scala.collection.immutable.List.foldLeft(List.scala:79)
at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
at freechips.rocketchip.system.RocketChipStage.run(RocketChipStageGenerator.scala:44)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
at firrtl.options.Translator.transform(Phase.scala:248)
at firrtl.options.Translator.transform$(Phase.scala:248)
at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183)
at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179)
at scala.collection.immutable.List.foldLeft(List.scala:79)
at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
at logger.Logger$.makeScope(Logger.scala:135)
at firrtl.options.Stage.transform(Stage.scala:47)
at firrtl.options.Stage.execute(Stage.scala:58)
at firrtl.options.StageMain.main(Stage.scala:71)
at freechips.rocketchip.groundtest.Generator.main(Generator.scala)
make: *** [Makefrag-verilator:13: /home/hengyu/zspace/cpu/rocket-chip/emulator/generated-src/freechips.rocketchip.groundtest.TraceGenConfig.fir] Error 1
```

**If the current behavior is a bug, please provide the steps to reproduce the problem:**
run `make CONFIG=TraceGenConfig` or `make CONFIG=freechips.rocketchip.groundtest.TraceGenConfig` in `rocket-chip/emulator`

**What is the current behavior?**
I try to make with TraceGenConfig but get errors.
Such as:
```
make CONFIG=TraceGenConfig

get error:
java.lang.Exception: Unable to find part "TraceGenConfig" from "List(TraceGenConfig)", did you misspell it or specify the wrong package path?
```

```
make CONFIG=freechips.rocketchip.groundtest.TraceGenConfig
or
make CONFIG=freechips.rocketchip.groundtest.TraceGenConfig MODEL=TestHarness PROJECT=freechips.rocketchip.groundtest

get error:
java.lang.IllegalArgumentException: requirement failed: Key TLNetworkTopologyLocat
ed(Location(InSubsystem)) is not defined in Parameters
```
**What is the expected behavior?**
Get an emulator with trace generator after make with TraceGenConfig.
**Please tell us about your environment:**
- version: `47f7b7144727f0340d511d35b9f6c7a91b2a276f`
- OS: `Linux 5.19.0-38-generic #39~22.04.1-Ubuntu SMP PREEMPT_DYNAMIC Fri Mar 17 21:16:15 UTC 2 x86_64 x86_64 x86_64 GNU/Linux`

**What is the use case for changing the behavior?**
Test memory, generate tarce and check by axe or other checkers.

Reproduce the emulator build using TraceGenConfig and the commands shown in the issue, then read scripts/tracegen.py and the stack-trace entry points around TestHarness, TraceGenConfig, and HasConfigurableTLNetworkTopology. Done means the configuration builds successfully and tracegen.py can generate the requested memory trace without the missing-parameter error.

Written by the indexing model from the issue text.