Cannot generate systems WithNSmallCores when L2 TLBs are enabled

**Type of issue**: bug report (?)

**Impact**: unknown

**Development Phase**: request

**Other information**

When building a Rocket system ```WithNSmallCores``` and enabling the L2 TLB by modifying the default ```nL2TLBEntries``` value, the following error appears:

```
Exception in thread "main" firrtl.passes.CheckWidths$BitsWidthException: @[PTW.scala 289:61]: [target ~TestHarness|PTW] High bit 26 in bits operator is larger than input width 21 in bits(r_req.addr, 26, 0).
```

The issue seems to come from the following code (introduced in #2841): https://github.com/chipsalliance/rocket-chip/blob/bf5742b9e353a80f501d43130218d3a444ec4b30/src/main/scala/rocket/PTW.scala#L289

which, in turn, is evaluated after this condition: https://github.com/chipsalliance/rocket-chip/blob/bf5742b9e353a80f501d43130218d3a444ec4b30/src/main/scala/rocket/PTW.scala#L269

This behavior can be only observed in 64-bit Rocket cores (i.e., extending the configuration ```WithRV32``` makes it disappear).

*Additional info: see the following (inconsistent?) parameters:* `addr` *in* `PTWReq` *and* `vpnBits` *in* `HasTileParameters` *versus* `maxSVAddrBits` *and* `pgIdxBits` *in* `HasNonDiplomaticTileParameters `.
https://github.com/chipsalliance/rocket-chip/blob/bf5742b9e353a80f501d43130218d3a444ec4b30/src/main/scala/rocket/PTW.scala#L20-L25
https://github.com/chipsalliance/rocket-chip/blob/bf5742b9e353a80f501d43130218d3a444ec4b30/src/main/scala/tile/BaseTile.scala#L161-L182
https://github.com/chipsalliance/rocket-chip/blob/bf5742b9e353a80f501d43130218d3a444ec4b30/src/main/scala/tile/BaseTile.scala#L60-L63

**If the current behavior is a bug, please provide the steps to reproduce the problem:**
Use the following configuration in rocket-chip:

```scala
package freechips.rocketchip.system
import freechips.rocketchip.config.Config
import freechips.rocketchip.subsystem._

class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
case other => other
}
})

class TestRocketConfig extends Config(
new WithL2TLBs(8) ++
new WithNSmallCores(1) ++
new BaseFPGAConfig)
```

Or use the following configuration in chipyard:

```scala
package chipyard
import freechips.rocketchip.config.Config

class TestRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
new chipyard.config.AbstractConfig)
```

*Note*: chipyard enables L2 TLBs [by default](https://github.com/ucb-bar/chipyard/blob/dcf8da4b2d3a4deead95462fce36a6db5693ed45/generators/chipyard/src/main/scala/config/AbstractConfig.scala#L48) in the ```AbstractConfig``` class.

**What is the current behavior?**
Cannot generate systems ```WithNSmallCores``` when L2 TLBs are enabled.

**What is the expected behavior?**
I would say that configurations using ```WithNSmallCores``` and setting ```nL2TLBEntries``` to anything different than 0 should work as they did in previous releases (i.e., before #2841, like chipyard 1.5.0) or when operating in 32-bit mode (i.e., ```WithRV32```).

However, the fact that this issue exists brings a couple of questions to my mind:
- Does it make sense to enable L2 TLBs when not using virtual memory?
- Is the problem described above the intended behavior? Am I missing something?
- Should this be reported in the chipyard repo instead (as it is indeed something that comes from its default configurations)?

**Please tell us about your environment:**

- version: bf5742b9e353a80f501d43130218d3a444ec4b30
- OS: `Linux alf-xps 5.4.0-100-generic #113~18.04.1-Ubuntu SMP Mon Feb 7 15:02:59 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux`

**What is the use case for changing the behavior?**
N/A

Start with the width calculation at src/main/scala/rocket/PTW.scala around lines 269 and 289, then compare the parameter definitions referenced in PTW.scala and src/main/scala/tile/BaseTile.scala. Reproduce the failure with WithL2TLBs and WithNSmallCores in the supplied configuration, including 64-bit mode. Done means the affected configuration generates successfully with L2 TLB entries enabled, while preserving the existing RV32 behavior.

Written by the indexing model from the issue text.