[Bug Report] Incorrect behavior of TileLinktoAHB module

**Type of issue**: bug report

**Impact**: API modification

**Development Phase**: request

**Other information**

**If the current behavior is a bug, please provide the steps to reproduce the problem:**
I use the TileLinktoAHB bus module to convert all AXI bus to AHB and run Gemmini with this configuration. Gemmini outputs correct values but a bug is encountered in the TileLinktoAHB process and noticed this bug that might affect others who are also using this module.

**What is the current behavior?**
The TileLinktoAHB module ignores the bit mask information and directly outputs whatever is on the `a_bits_address`.
**What is the expected behavior?**
The hsize and haddr should be affected by a_bits_mask which contains the bit mask information.

TileLinktoAHB module is not taking into account of the bit mask information. From the below waveform graph (top module is from Gemmini, bottom is TileLinktoAHB), the correct behavior should be: `hsize`/`haddr `changes according to `a_bits_mask ` so that only the portion of `8000_c9a0 ` that's not masked by `a_bits_mask` is output to `haddr `. but you can see that TileLinktoAHB is not taking into account of the bit mask information. The scala code that needs to be modified is probably somewhere here : https://github.com/chipsalliance/rocket-chip/blob/400f99530790a0e149f4d9b52b7ddbcafd41c653/src/main/scala/tilelink/ToAHB.scala#L153 .

Start in src/main/scala/tilelink/ToAHB.scala around line 153 and inspect how TileLinktoAHB derives hsize and haddr from a_bits_address. Reproduce the reported Gemmini configuration and compare the waveform against a_bits_mask. Done means hsize and haddr reflect the unmasked portion of the address.

Written by the indexing model from the issue text.