chipsalliance / chipsalliance/rocket-chip

Setting mulDiv = None still instantiates a multiplier-divider

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bug build: scala/chisel/firrtl needs new testing
Dominant language
Scala
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Description

**Type of issue**: bug report

**Impact**: unknown

**Development Phase**: request

**Other information**

**If the current behavior is a bug, please provide the steps to reproduce the problem:**
**What is the current behavior?**

Setting mulDiv = None or using the provided WithoutMulDiv configuration still instantiated a multiplier-divider. This is a problem as Quartus 20.1 fails to optimize it away and the multiplier becomes the critical path of the design.

**What is the expected behavior?**

Not instantiating the multiplier-divider when mulDiv = None.

**Please tell us about your environment:**

git commit hash: a7b016e46e22e4fdc013357051e30511f80df082
OS: Ubuntu 20.04 on WSL 2

**What is the use case for changing the behavior?**
Achieving high operating frequency on an Intel FPGA when the hard multiplier-divider is not required.

Contributor guide

Open the contributing guide

Research direction

Trace the mulDiv configuration and the provided WithoutMulDiv configuration from their definitions to where the multiplier-divider is instantiated. Reproduce the configuration on the reported Rocket Chip commit and inspect the generated design; done means mulDiv = None does not instantiate the multiplier-divider and the affected FPGA critical path is removed.

Written by the indexing model from the issue text.

Assessment

Tech stack
scala
Domain
embedded-iot
Issue type
Bug
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
38/100

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