chipsalliance / chipsalliance/rocket-chip
nTLBBasePageSector variable mean with respect to TLB
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- Scala
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Description
I am having confusion of understanding this variable in Hellacache.scala. We have
case class DcacheParams and in thar we are setting TLB parameters I am unable to understand the variable meaning
nTLBBasePageSector:Int =4
And why we are setting it to 4?
For your reference I have also attached the file snippet below
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