How are parent and child lazymodule's clock and reset are connected?

Every chisel module has implict clock and reset, I wonder if the parent and child's clock and reset are automatically connected?
Also, I wonder if parent and child **lazymodule's** clock and reset are connected by default(considering the module property of Lazymodule is LazyModuleImp, I know if the module of LazyModule is of type LazyRawModuleImp, then you can wire the child clock and child reset manully. I just felt confused about the default behavior)? If they are connected, which part of the code base indicate this?
Thanks!
Part of this is a chisel question, So @jackkoenig, can you clarify this for me?
@hcook @terpstra

The issue names LazyModule, LazyModuleImp, and LazyRawModuleImp but no file or test. Start by tracing those entry points in the rocket-chip codebase and checking the related Chisel behavior. Done means documenting whether parent and child clocks and resets are connected by default, with the relevant code location identified.

Written by the indexing model from the issue text.