DebugAPB Generation Error

**Type of issue**: bug report

**Impact**: no functional change | API addition (no impact on existing code) | API modification | unknown

**Development Phase**: request

**Other information**
I have been using the rocket-chip generator for personal fun. But when trying to generate DebugAPB Interface, it appears the error message with "empty.init" output. I tried to debug the error message, but could not go further on this. Also when googling, there are some having same trouble with me.

**If the current behavior is a bug, please provide the steps to reproduce the problem:**
With fresh repository clone in my local directory, I put the "WithDebugAPB ++" in system/Configs.scala, class DefaultConfig. After generating in vsim directory, the error message as above comes out.
**What is the current behavior?**
Current rocket-chip verilog generation Environment can't make verilog files with debug APB Interface. Only able to generate the JTAG Interface with on. It seems there was the delete of the memory map files on debug module with APB regmapper. I suspect on that because the error log shows the RegMapper has empty init interface.

**What is the expected behavior?**
The final generated verilog file needs to have APB Interface to access RISC-V Debug Module.
**Please tell us about your environment:**

**What is the use case for changing the behavior?**

Start with system/Configs.scala, the DefaultConfig class, and the WithDebugAPB setting. Reproduce the generation from a fresh clone in the vsim directory, then follow the reported RegMapper empty.init error. Done means the generator produces Verilog containing an APB interface for the RISC-V Debug Module.

Written by the indexing model from the issue text.