chipsalliance / chipsalliance/rocket-chip
Mem-AXI malfunctions
- Dominant language
- Scala
- Stars
- 3.9k
- Forks
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- Avg merge
- 5d 13m
- Merged PRs (30d)
- 1
Description
I'm building a shell on VC707 (not _sifive/freedom_ repo). My system works well when the address map can be represented in 32-bit.
However, if not, it fails to copy the BBL to DRAM during FSBL.
I just modified parameters in _src/main/subsystem/Config.scala_. Should I modify other files?
Contributor guide
Research direction
Start with src/main/subsystem/Config.scala and review the address-map parameters used by the FSBL path that copies BBL to DRAM. Reproduce the failure with an address map that cannot be represented in 32 bits, then compare it with the working 32-bit configuration. Done means the BBL copy succeeds on the VC707 setup without breaking the existing 32-bit case.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100