System hangs after AXI4-Lite register read

I want to connect an IP core with AXI4-Lite in SiFive Freedom Unleashed (using branch bump-stuff) on the VCU118. For simplicity I test with the Xilinx AXI GPIO.

Snippets how the GPIO IP core is connected to the peripheral bus:

```
val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(BigInt(0x64090000L), 0x10000-1L)),
resources = gpio.reg,
supportsWrite = TransferSizes(1, 4),
supportsRead = TransferSizes(1, 4),
interleavedId = Some(0))),
beatBytes = 4)))
```
```
val slave: TLInwardNode =
(gpio.slave
:= AXI4Buffer()
:= AXI4UserYanker(capMaxFlight = Some(1))
:= TLToAXI4(adapterName = Some("gpio"))
:= TLFragmenter(4, p(CacheBlockBytes), holdFirstDeny = true))
```
`pbus.coupleTo(s"gpio") { gpio.get :*= TLWidthWidget(pbus.beatBytes) :*= _ }`

I can do writes to a GPIO register without a problem (I use the LEDs on the board for testing). But as soon as I read a register (getting the correct result) the system hangs. When I change `AXI4UserYanker(capMaxFlight = Some(1))` to `AXI4UserYanker(capMaxFlight = Some(2))`, I can do 2 reads before the system hangs. To me it looks like the AXI4UserYanker collects the requests and does not release them again. The GPIO IP cores AXI4-lite does not use IDs (ID_width=0), is that a problem?

I tested this with read/write registers via JTAG, with a bare-metal application and with linux, always the same result. I looked at the AXI signals with an ILA and both reading and writing look good.

I would be glad about hints and ideas what the problem could be. Thanks!

Start by reproducing the register-read hang through the AXI4 GPIO connection, using the JTAG, bare-metal, or Linux paths mentioned in the report. Read the AXI4UserYanker and TLToAXI4 integration points and compare ILA traces for one versus two outstanding reads. Done means identifying why completed reads are not released and verifying that repeated reads no longer hang.

Written by the indexing model from the issue text.