Parameterize RISC-V Tests Collateral Generation

Changing the base address of memory will break all regression tests. This is due to the base address being hard-coded inside the linker scripts of `riscv-tests` for both ISA tests and benchmark tests. E.g., [riscv-test-env linker.ld](https://github.com/riscv/riscv-test-env/blob/2f75dc2940f1f780b1f2d12f41daec9c92fc445a/p/link.ld#L6) sets the base address to `0x8000_0000` and this will fail if you place main memory at `0x9000_0000` even though this is a legal Rocket Chip parameterization and just changing the linker script will get tests to pass.

It would be cool if the appropriate linker script was generated as part of the SoC generation process and the associated test suite makefile fragments would then also compile the appropriate tests.

There is likely a similar generation solution with the boot ROM and it's linker script.

It appears that what I'd like is something like direct integration with one of the SiFive tools for generating linker scripts like:

- https://github.com/sifive/ldscript-generator
- https://github.com/sifive/freedom-devicetree-tools

I quickly tried these with the vanilla Rocket Chip DTS (or a DTB version of the generated DTS), but wasn't able to get them to work.

**Type of issue**: feature request

**Impact**: no functional change

**Development Phase**: request

**Other information**

None.

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

Change the base address of memory and do a `RISCV=??? make -C emulator run-regression-tests-fast`. The design will hang or fail.

**What is the current behavior?**

Regression tests are symlinked from the `$RISCV` install location.

**What is the expected behavior?**

The tests should be linked into the correct place in memory based on the base address of main memory.

**Please tell us about your environment:**

`master`

**What is the use case for changing the behavior?**

This would improve the automatic ability of Rocket Chip to test SoC designs with non-default memory maps.

Start with the riscv-test-env linker.ld example and the emulator target `run-regression-tests-fast`; trace how SoC generation exposes the memory base and how regression tests are selected from `$RISCV`. Compare the suggested SiFive linker-script and device-tree tools, and consider the boot ROM linker script too. Done means generated linker scripts and test makefile fragments use the configured memory address.

Written by the indexing model from the issue text.