128-bit memory interface ( L2 cache interface)- Rocket RoCC accelerator

**Type of issue**: Rocc Memory interface (L2 cache interface)

The question is about 128-bit memory interface ( L2 cache interface) Rocket-Rocc interface :

Current example Rocket-Chip-RoCC/src/main/scala/tile/LazyRoCC.scala include 64-bit memory interface however I need to transfer 128-bit data into accelerator from memory,
Do I need to transfer 128-bit data to the accelerator is there any such example ?

or
How can I transfer 128-bit data from memory to RoCC accelerator

Thanks

Start with Rocket-Chip-RoCC/src/main/scala/tile/LazyRoCC.scala and inspect how its existing 64-bit memory interface is connected to the accelerator. Determine whether the requested 128-bit memory transfer is supported and what interface or example would be needed; done should mean a defined 128-bit path or a clear documented limitation.

Written by the indexing model from the issue text.