chipsalliance / chipsalliance/rocket-chip
AXI4.B channel could be abnormally blocked by TLToAXI4
- Dominant language
- Scala
- Stars
- 3.9k
- Forks
- 1.3k
- Avg merge
- 5d 13m
- Merged PRs (30d)
- 1
Description
**Type of issue**: other enhancement
**Impact**: functional change
**Development Phase**: proposal
**Other information**
**If the current behavior is a bug, please provide the steps to reproduce the problem:**
- Environment: 5 AXI4 Masters are connected to 1 AXI4 slave through TLXbar
- 4 of AXI4 masters issues 100Kbytes read-burst transactions(ARLEN=7, max-outstanding=16)
- 1 of AXI4 masters issues 100Kbytes write-burst transactions(ARLEN=7, max-outstanding=16)
==>
**What is the current behavior?**
The AXI4 master(writing) could not get AXI4.B response until the other 4 masters have done.
TLToAXI4 gives priority to read-response(AXI4.R), it is fixed priority.
So, a bunch of read-transactions could block all of AXI4.B response channel transactions abnormally.
**What is the expected behavior?**
I propose that AXI4.B channel get a chance to win whenever a read response has done.
**Please tell us about your environment:**
- version: 7c072e9999a1be4028aed383dcf97b03e2773988
- OS: CentOS Linux 7 (Core)
**What is the use case for changing the behavior?**
Contributor guide
Research direction
Start at TLToAXI4 and inspect the arbitration between AXI4.R and AXI4.B responses. Reproduce the five-master workload described in the issue, then verify that repeated read responses no longer prevent the writing master from receiving its B response.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100