chipsalliance / chipsalliance/rocket-chip
mtval not written after ebreak
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- Dominant language
- Scala
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Description
Type of issue: bug report
Impact: unknown
Development Phase: proposal
Other information
Spec says mtval register is written with the faulting virtual address when a hardware breakpoint is triggered, but Rocket chip does not save the address to mtval register when ebreak instruction is executed. Is it intended?
Here's all my test and logs as before.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reviewing the RISC-V behavior described in the issue and reproducing the report with the attached test.zip and its logs. Trace how Rocket Chip handles ebreak and writes mtval, then verify the result against the cited specification; done means the reported mtval behavior is corrected or its intended behavior is documented.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Active
- Clarity
- Mostly clear
- Newbie friendliness
- 48/100