chipsalliance / chipsalliance/rocket-chip
Glitch on Asynchronous Reset of AsyncQueue.scala
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question
- Dominant language
- Scala
- Stars
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Description
In Asynchronous Queue Line 99:
source_valid.reset := reset.asBool || !sio.sink_reset_n
Asynchronous reset signal of source_valid is driven by a combinational logic. There is a possibility of glitch on the reset signal. Am I missing something?
There are many places with same errors in AsyncQueue.scala
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Read AsyncQueue.scala around line 99 and inspect the other locations with similar reset assignments. Determine whether the combinational reset paths can glitch, then confirm the appropriate scope of the fix and validate the result with the repository's relevant AsyncQueue coverage.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- embedded-iot, tooling
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100