make: *** [output/multiply.riscv.out] Error 1

**Type of issue**:
When i use the VCS to simulate the generated instruction in the vsim/output, i have some problems.
The errors are as follows.
/home/user/Original_risc-v/tmp_rocketchip/rocket-chip/vsim/Makefrag-verilog:34: recipe for target 'output/multiply.riscv.out' failed
make: *** [output/multiply.riscv.out] Error 1
make: *** Waiting for unfinished jobs....
/home/user/Original_risc-v/tmp_rocketchip/rocket-chip/vsim/Makefrag-verilog:34: recipe for target 'output/towers.riscv.out' failed
make: *** [output/towers.riscv.out] Error 1
/home/user/Original_risc-v/tmp_rocketchip/rocket-chip/vsim/Makefrag-verilog:34: recipe for target 'output/median.riscv.out' failed
make: *** [output/median.riscv.out] Error 1
/home/user/Original_risc-v/tmp_rocketchip/rocket-chip/vsim/Makefrag-verilog:34: recipe for target 'output/vvadd.riscv.out' failed
make: *** [output/vvadd.riscv.out] Error 1
/home/user/Original_risc-v/tmp_rocketchip/rocket-chip/vsim/Makefrag-verilog:34: recipe for target 'output/mt-matmul.riscv.out' failed
make: *** [output/mt-matmul.riscv.out] Error 1
/home/user/Original_risc-v/tmp_rocketchip/rocket-chip/vsim/Makefrag-verilog:34: recipe for target 'output/dhrystone.riscv.out' failed
make: *** [output/dhrystone.riscv.out] Error 1
/home/user/Original_risc-v/tmp_rocketchip/rocket-chip/vsim/Makefrag-verilog:34: recipe for target 'output/qsort.riscv.out' failed
make: *** [output/qsort.riscv.out] Error 1

But importantly, i try the single instruction's test in the VCS, but the pc in the core are wrong and it's not related to the disassembly code, such as the base address 0x80000000

**Development Phase**:
ensure the all instructions passed

**What is the expected behavior?**
How can i complete the instructions' compiler?
And use Synopsys DVE&&VCS to simulate the whole project?

**Please tell us about your environment:**
<
-Simulation software: Synopsys DVE&&VCS 2016
- OS: `Linux Ubuntu 16.04`
-->

Who can help me? Thanks a lot!

Start at vsim/Makefrag-verilog:34 and reproduce the single-instruction and whole-project runs with Synopsys VCS/DVE on Ubuntu 16.04. Gather the compiler and simulator output beyond the make summary, then compare the reported PC with the expected 0x80000000 base address. Done means the instructions compile and the listed tests simulate successfully.

Written by the indexing model from the issue text.