Synthesizing to FPGA

When I generate Verilog to target FPGA, a 'ram' reg is generated (plz see below) which is much too large to fit in any typical FPGA BRAMS during synthesis. Is that normal or a glitch of some sort at my end? I reduce it extremely just to see synthesis through, but I am not really sure what am I doing and what does it affect.

module mem_ext(
input W0_clk,
input [24:0] W0_addr,
input W0_en,
input [63:0] W0_data,
input [7:0] W0_mask,
input R0_clk,
input [24:0] R0_addr,
input R0_en,
output [63:0] R0_data
);

reg reg_R0_ren;
reg [24:0] reg_R0_addr;
reg [63:0] ram [33,554,431:0]; //this is much too large!
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 33554432; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_R0_addr = {1 {$random}};
end
`endif

Begin with the posted mem_ext Verilog and the FPGA synthesis report. Trace how the 25-bit W0_addr/R0_addr widths and ram declaration are produced, then compare the generated memory size with the intended configuration. Done means determining whether this is expected generation or a defect and recording the relevant configuration or reproduction.

Written by the indexing model from the issue text.