chipsalliance / chipsalliance/rocket-chip
question -- spliting the MMIO form the output of the hellacache
- Dominant language
- Scala
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- 5d 13m
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- 1
Description
```
val node = TLClientNode(Seq(TLClientPortParameters(
cacheClientParameters ++ mmioClientParameters,
minLatency = 1)))
```
```
trait HasHellaCache { this: BaseTile =>
val module: HasHellaCacheModule
implicit val p: Parameters
def findScratchpadFromICache: Option[AddressSet]
var nDCachePorts = 0
require(tileParams.dcache.get.nMSHRs > 0)
lazy val dcache: HellaCache = LazyModule(
if(tileParams.dcache.get.nMSHRs == 0) {
new DCache(hartId, findScratchpadFromICache _, p(RocketCrossingKey).head.knownRatio)
} else { new NonBlockingDCache(hartId) })
tlMasterXbar.node := dcache.node
```
in this part the node contains both the cache and the MMIO I would like to split these into 2 different tilelink nodes
what's the best way to do that ?
thanks a lot
Contributor guide
Research direction
Start by reading HasHellaCache, the dcache.node connection, and the TLClientNode construction shown in the issue. Trace how cacheClientParameters and mmioClientParameters are combined, then identify the project’s existing TileLink node patterns. Done means the cache and MMIO paths are exposed through separate TileLink nodes without losing the required connections.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 25/100