chipsalliance / chipsalliance/rocket-chip

How can I managed the physical memory cacheability setting for a memory region in machine mode software

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question
Dominant language
Scala
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Avg merge
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Merged PRs (30d)
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Description

**Type of issue**: bug report | feature request | other enhancement

**Impact**: no functional change | API addition (no impact on existing code) | API modification | unknown

**Development Phase**: request | proposal

**Other information**

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

**What is the current behavior?**

**What is the expected behavior?**

**Please tell us about your environment:**

**What is the use case for changing the behavior?**

Contributor guide

Open the contributing guide

Research direction

The issue names no files, tests, reproduction steps, environment, or expected behavior. Start by clarifying whether this is a feature request or a support question, then provide a concrete cacheability use case and affected Rocket Chip configuration. The scope and definition of done cannot be established until those details are supplied.

Written by the indexing model from the issue text.

Assessment

Tech stack
scala
Domain
embedded-iot
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
10/100

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