Dcache Signals

Hi,
I am trying to understand the Dcache.scala code. i am new to chisel.
I am trying to figure out the signals generated for a cache miss in Dcache.
What I understand is that s2 is the request from the core which is 2 clock cycles prior and s1 is the request 1 cycle prior.
I was wondering at a given time, which signal is generated for a cache miss, is it s2_valid_cache_miss?
Which request should I focus in case of the current request?
Any suggestion will be appreciated!
Thanks!
Nilufar

Start by reading Dcache.scala and trace the s1 and s2 request signals, including s2_valid_cache_miss. Compare their timing with the issue's description of requests from the core. Done means documenting which signal represents the current cache-miss request and how the related signals should be interpreted.

Written by the indexing model from the issue text.