Generate tests that use the same register more than once

Currently, generated vector instructions will use a distinct `vd`, `vs2`, and `vs1`. However, as I had to find out, it's easy to introduce bugs in an RVV implementation that only manifest when a register is used more than once, especially when `vd` is also a source register.

Thus, I suggest adding tests that cover that scenario.

Start by reading the generator and its existing vector-instruction test generation to see how vd, vs2, and vs1 are selected. Add generated cases where registers are reused, including cases where vd is also a source register, and verify the resulting tests cover those scenarios.

Written by the indexing model from the issue text.