chipsalliance / chipsalliance/i3c-core
Sync Reset Support
Open
Future
- Dominant language
- SystemVerilog
- Stars
- 57
- Forks
- 35
- PR merge metrics
- No merged PRs in 30d
Description
Can we please get a version of I3C that uses sync resets? This would simplify both your design and integrator's designs if we use sync resets instead of async.
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