chipsalliance / chipsalliance/fasm

Create VPR arch and rrgraph linting tools

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Dominant language
Python
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Description

Currently FASM annotations errors are detected late in the flow. A tool to sanity check VPR arch and rrgraph annotations would allow earlier error detection, and cross linking with Verilog blackbox definitions.

Suggested lint passes:
- [ ] Error if FASM mux definition defines an input that does not exist
- [ ] Error if FASM mux definition does not an input that is specified in the mux/direct tag
- [ ] Warning if FASM params definition is missing a parameter defined in the Verilog module
- [ ] Error if FASM params definition defines a parameter that does not exist in the Verilog module
- [ ] Error if the bit width of the FASM params definitions does not match the Verilog module parameter width
- [ ] Error if FASM prefix length does not match num_pb value
- [ ] Error if FASM annotation generates a FASM tag that does not exist
- [ ] Error if FASM lut annotation is missing on a class="lut" or subckt=".names" black box.
- [ ] Error if FASM annotation is illegal (e.g. syntax error)

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