chipsalliance / chipsalliance/f4pga-examples
USB3.0 PHY / PIPE example?
Open
- Dominant language
- Verilog
- Stars
- 289
- Forks
- 79
- PR merge metrics
- No merged PRs in 30d
Description
- https://github.com/enjoy-digital/usb3_pipe compiled with Vivado
- https://github.com/enjoy-digital/daisho compiled with SymbiFlow
Kind of like that PCIe demo you did previously.....
Contributor guide
No contributing guide indexed for this repository
Research direction
Start by comparing the linked usb3_pipe and daisho repositories, then review the previous PCIe demo referenced in the issue and this repository’s example conventions. Clarify the intended USB 3.0 PHY/PIPE target and toolchain flow; done should be a reproducible example comparable to those references.
Written by the indexing model from the issue text.
Assessment
- Domain
- build-system, embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100