Question: Possible to test tools without .xdc file?

When a design won't go through the tools it would be nice to be able to narrow down the issue by only compiling the individual module with the problem and posting the results with the issue. However, to do so requires an .xdc file be created, which is painstaking for modules with lots of I/O. Case in point: we have a simple memory module failing synthesis, presumably because Yosys doesn't like BRAM code with conditional reads. The small module in question (embedded in the bigger design) has, maybe, 8 lines of behavioral code but 60+ bits of I/O.

In Vivado there is a Tcl directive that says, essentially: "Don't complain about unmapped I/O" so that you can quickly synthesize such modules.

Does f4pga-examples have any way to do this? It would make providing examples of modules that are failing the front end tools much easier... I do realize that at some point you need to have mapped I/O for the remainder of the tool flow to complete, but when the problem is a synthesis/techmapping problem having such a capability would be quite useful...

No files, tests, or entry points are named. Start by locating the example flow that invokes synthesis and checking how .xdc constraints are required; done would be a documented or implemented way to synthesize an isolated module without manually creating full I/O constraints.

Written by the indexing model from the issue text.