chipsalliance / chipsalliance/f4pga-examples

Symbiflow-classroom: Array Initializers Do Not Work

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classroom
Dominant language
Verilog
Stars
289
Forks
79
PR merge metrics
No merged PRs in 30d

Description

SYMBIFLOW-CLASSROOM-PROJECT

Using original Yosys frontend.

If SV code contains a legal array declaration and initialization like this:
```
// Lookup table for % 3 calculation.
logic[1:0] modmem[8] = '{0, 1, 2, 0, 1, 2, 0, 1};
```
a syntax error results. Arrays cannot be initialized this way with the tools (but it is legal SV and works with other tools).

Contributor guide

No contributing guide indexed for this repository

Research direction

Start by reproducing the SystemVerilog array initializer with the original Yosys frontend, using the example in the issue. Trace where the legal declaration and initialization is rejected; done means this form is accepted without a syntax error and existing relevant checks still pass.

Written by the indexing model from the issue text.

Assessment

Domain
compilers
Issue type
Bug
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
35/100

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