chipsalliance / chipsalliance/dromajo
Rewamp device model
- Dominant language
- C++
- Stars
- 244
- Forks
- 69
- PR merge metrics
- No merged PRs in 30d
Description
This is forked off @ss2783's pull request #15 where extending the CLINT to handle sub-word accesses ran into trouble.
The fundamental problem is that the device model is currently called upon the load/stores directly and it's up to the handler to deal sub-word handling.
I think there's a model that works better:
1. Allocate backing store (RAM) to the address space taken by the device
2. All loads and stores just read the backing store as normal memory
3. There's an optional pre-read hook which is called with hints about the access address and size.
Devices without read side-effects don't need to provide this hook.
4. There's an optional post-write hook which is called with hints about the access address and size.
Devices without write side-effects don't need to provide this hook.
5. There's an optional timer callback that can be registered to be called for every N ticks. Alternatively, it can schedule itself on a as-needed basis, TBD.
This significantly reduces the amount of code that needs to be written to support most devices and removes the sub-word access handling from devices (unless they really want to handle this in a special way).
Contributor guide
No contributing guide indexed for this repository
Research direction
Review pull request #15 first, then trace the current device-model load/store handlers and the CLINT path to understand how sub-word accesses are handled. Done means the device model supports backing storage with optional pre-read, post-write, and timer hooks, while ordinary loads and stores use the backing store.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- devtools
- Issue type
- Refactor
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100