Feature discussion | Generating SystemVerilog assertions from Chisel

**Type of issue**: other enhancement

**Impact**: API addition (no impact on existing code)

**Development Phase**: request

Just wanted to ask the community if there would be any value in being able to write SystemVerilog assertions in Chisel, and then getting them synthesized in the generated Verilog?

I am quite inexperienced in the area of HDL's and verification approaches out there. But after watching a talk on Block Level formal verification at the Chisel User's Group, I assume it would be useful if you could specify the SystemVerilog assertions on high level objects like Chisel bundles, and then accordingly they would get generated. This could help in plugging it into JasperGold, Yosys-SMTBMC sort of bounded model checks.

Wanted to know the communities thoughts!