Real Verilog tables from Chisel Vecs

Tables in Chisel are Vecs, but the Verilog output generates a priority MUX. This leads to the fact that Chisel generated tables result in LUT logic in an FPGA although they can be implemented in on-chip memory. This needs more resources and has a lower maximum frequency.

In my tutorials on Chisel I usually mention it as a big advantage that we can use Scala to generate logic tables, e.g., for microcode for a state machine, code for a processor, or a lookup table for functions. All those large tables should end up in a on-chip RAM in an FPGA.

Therefore, I request that tables (Vecs) generate a case statement that is understood by FPGA synthesize tools to generate on-chip ROM.

I've put up an example of a 1 KB table to illustrate the case:

git clone https://github.com/schoeberl/chisel-playground.git

cd chisel-playground
make table-verilog

and run the synthesize with Intel Quartus (from quartus/issue-table.qpf) for a real Verilog table.

Results:

10 logic elements and 8192 memory bits, fmax 250 MHz (restricted to this)

Generate the Chisel based table with:

make table-chisel

and synthesize:

870 logic elements, no memory bits, fmax 191 MHz

As long as (Quartus) synthesize tools cannot extract a simple lookup table from priority MUX code, I strongly propose that Chisel/FIRRTL shall spill out a case based table for a Vec.

Cheers,
Martin