chipsalliance / chipsalliance/chisel
[RFC] Bits as full Types
- Dominant language
- Scala
- Stars
- 4.8k
- Forks
- 658
- Avg merge
- 18h 59m
- Merged PRs (30d)
- 14
Description
Bits in Chisel are currently second-class citizens. This is different from Chisel 2, where more functions with Bits are available. Therefore, the reduced functionality of Bits creates a compatibility issue with Chisel 2.
Besides that, Bits as type has a merit on its own (see below).
**Type of issue**: feature request
**Impact**: API addition (no impact on existing Chisel 3 code), but improves Chisel 2 compatibility
**Development Phase**: proposal
Not all data types in hardware are signed or unsigned integers. For example, a word in memory may be an integer, an instruction, or a floating point values. Or something else. Representing this word as UInt is not the correct type. The same is true for a register in a processor, the data field in a bus, and more.
For stronger typing, it makes sense to have a complete Bits type. Bits shall be a collection of bits without an arithmetic meaning. Allowed operations are logical functions (&, |, ^, ~), reduction, and comparison (===, =/=). There is no place for addition or < comparison. Bits can be cast to an integer type.
One question is, how bit vectors with different widths are handled. Either automatic expansion as for UInt or having the length as part of the Bits type and disallow operations with different lengths. The later would be a stronger type restriction. If easy to implement, the later is preferable.
When looking at VHDL as an example language, there are three types: std_logic_vectore, which has no arithmetic operations, unsigned, and signed. Bits would be the equivalent of std_logic_vector.
Bits can be lowered to UInt in FIRRTL and then Verilog without losing the additional type safety in Chisel 3.
Contributor guide
Research direction
No files, tests, or entry points are identified in this proposal. First clarify the Bits API and width semantics, then trace how Bits would lower to UInt in FIRRTL; done means the logical and comparison operations, integer casting, and Chisel 2 compatibility behavior are specified and tested.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100