Request for a NotSynthesized annotation on a per signal basis.

**Type of issue**: feature request

**Impact**: API addition (no impact on existing code)

**Development Phase**: request

**What is the use case for changing the behavior?**

There are useful signals to add for debug and verification that would be too expensive to synthesize.

**What is the expected behavior?**

I would like some way to annotate Chisel nodes/signals/registers as "NotSynthesized"/"DontSynthesize"/whatever.

Chisel/firrtl currently uses the define macro SYNTHESIS to gate off unsynthesized logic. Regarding the final code generation, perhaps one of two things can happen in the Verilog:

1) Hide unsynthesized nodes behind a `ifndef SYNTHESIS` macro. This is probably not possible since I guess every use of these signals would also have to be gated off or else it would throw undefined errors.

2) Throw an error if SYNTHESIS is set and NotSynthesized signals exist in the Verilog code. This is weird (does Verilog have require statements?), and would put the burden on the Chisel RTL user to disable/remove NotSynthesized code from their design once they want to take the design through synthesis, but it helps catch mistakes (esp. when using someone else's code).

This is a bit pie-in-the-sky so I'd be interested in hearing other people's thoughts on this.