chipsalliance / chipsalliance/chisel
[RFC] More Consistent Notion of "Infinite Width" Values
- Dominant language
- Scala
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Description
Discussion originated in https://github.com/freechipsproject/chisel3/pull/857. The motivating example is bit extraction for literals of unspecified width. For example:
```scala
for (i <- 0 until 4) {
io.out(i) := io.in(i) && 5.U(i)
}
```
Here I'm using the literal `5.U` as a numerical value, I don't care about the width. However, without the special-case support in #857 this would result in an out-of-bounds indexing error. A more consistent notion would be helpful because the existing implementation that works for literals does not work for other Chisel values like Wires, Registers, nor Ports.
#### Sketch of Proposal
As discussed in the Chisel developers meeting on July 27th, we could create a new Chisel API (and corresponding FIRRTL primop) that does something like `padToInfinity` or `padUnbounded`. The full implications of such an operation are not clear, but at least in the case of bit select, the argument would be treated as if it were zero- or sign-extended to infinity. I imagine we need to think through exactly how this influences width inference (if at all).
#### PR Template
**Type of issue**: feature request
**Impact**: API modification*
It's hard for me to see how we do this in a principled way without some sort of API modification. The extend of it remains to be seen.
**Development Phase**: request
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