Chisel Standard Library

So the standard library we currently have (chisel3.utils) is kind of haphazard, incomplete, and in some cases, inelegant and confusing (I'm looking at you, Counter...)

This issue is just to start the conversation on what we want in a standard library. Ideally, these should be highly-reusable parts, and kind of following in Python's philosophy of "batteries included".

Some may already exist elsewhere (most notably, in [rocket-chip](freechipsproject/rocket-chip)'s various utilities), the goal here would be to make it easy to use those bits without importing the monster that is rocket. A standard library would also carry the expectation of stability.

## Standard library thoughts
I'll start off a list here. It's not complete or exhaustive, just a starting point for discussion. **Please add more suggestions in the comments!**

### Async utils
- Clock crossing FIFOs
- Clock dividers
- PLL templates, generating into FPGA blocks or blackboxes

### Communications utils
- Digital CDR blocks
- Encoders / decoders: 8b/10b, 64b/66b, NRZ, ...
- Standardized interfaces: JTAG, boundary scan, ...
- Standardized communication protocols: USB (2.0 | 3.0), SD card, Ethernet, PCIe, ...
- Standardized inter-chip protocols: I2C, SPI, UART, ...
- On-chip busses: TileLink, AXI, ...
- CRC generator

### Processing
- All the DSP stuff, with a standardized interface

### Physical interfaces
- FPGA blocks, including output drivers, input buffers, tristate drivers, and associated bundles (like a Tristate bundle)
- DDR/DDR2/etc interfaces

### Other
- Most of the stuff we have in the current chisel3.utils package, but probably cleaning up the interface a bit. API breakages can be avoided by deprecating what we have right now in favor of a different package, like chisel3.stdlib (or something)
- Efficient SRAM versions of things like registers and queues

## Issue Data

**Type of issue**: feature request

**Impact**: API addition (no impact on existing code)

**Development Phase**: request

**Other information**