Support for system verilog interfaces in BlackBox modules

Currently as far as I can tell there is no good way of wrapping a system verilog module with the "BlackBox" mechanism. While it is in principle possible to write adapter modules that have plain verilog ports on one side and system verilog interfaces on the other, it would be desirable to be able to wrap system verilog modules directly.

* **Type of issue**
- [ ] Bug report
- [x] Feature request
- [ ] Other enhancement

* **What is the use case for changing the behavior?**

Easier integration of chisel modules in existing system verilog code bases.

* **Impact**
- [x] API addition (no impact on existing code)

* **Development Phase**
- [x] request
- [ ] proposal