Vec of Module IO strips directions and can connect to Bundle with different directions

Consider the following:
```scala
class PassthroughModule extends Module {
val io = IO(new Bundle{
val in = Input(UInt(32.W))
val out = Output(UInt(32.W))
})
io.out := io.in
}

class FakePassthroughModule extends Module {
val io = IO(new Bundle{
val in = Input(UInt(32.W))
val out = Input(UInt(32.W))
})
}

class TestCase extends BasicTester {
val vm = Vec.fill(1)(Module(new PassthroughModule).io)
val m = Module(new FakePassthroughModule)

vm(0) <> m.io
}
```

Despite PassthroughModule and FakePassthroughModule having different directions, the Vec strips directions so this connection succeeds. Frighteningly, it even goes through Firrtl and emits valid Verilog.