chipsalliance / chipsalliance/chisel
MultiClockSpec chiselTest fails with recent Verilator version
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Description
**Type of issue**: Bug Report
**Please provide the steps to reproduce the problem:**
Install Verilator >= v5.046, then run `./mill chisel[].test.testOnly chiselTests.MultiClockSpec`
```
[40] %Error: ClockDividerTest_Verification_Assert.sv:72: Assertion failed in TOP.svsimTestbench.dut.verification_assert: Assertion failed at MultiClockSpec.scala:26
```
Problem not flagged by CI, because the Chisel CI pipeline uses a nightly build from verilator, provided by oss-cad-suite on 2023-06-21.
```
./verilator --version
Verilator 5.013 devel rev v5.012-12-g9ee5fd058
```
I confirmed that the testcase passes if using Verilator <= v5.044.
**What is the expected behavior?**
The ClockDividerTest should pass, independent of simulator version.
**Please tell us about your environment:**
Verilator v5.046 on linux-x64.
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