chipsalliance / chipsalliance/chisel

Analog type does not allow static addressing of sub-wires

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#536 3 comments 0 reactions 1 assignee Claimed by @jackkoenig View on GitHub
Feature feature request
Dominant language
Scala
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Merged PRs (30d)
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Description

For example, if you have a 4-bit wide Analog bus and want to route each wire to separate blocks, you cannot do the following:

...
val myWire = Analog(4.W)
...
val bb = Module(new MyBlackBox())
attach(bb.io.myWire,io.myWire(3))
...

It looks like an apply(x: Int) method like in Bits would be sufficient.

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