"-disable-all-randomization" can't work when the module with RequireAsyncReset

**Type of issue**: Bug Report
"-disable-all-randomization" can't work when the module with RequireAsyncReset

**Please provide the steps to reproduce the problem:**
my test code like this >>>>

import chisel3._
import circt.stage.{ChiselStage, FirtoolOption}

//class Hello extends Module with RequireAsyncReset {
class Hello extends Module{
val io =IO(new Bundle {
val led = Output(UInt(1.W))
})
val CNT_MAX = (50000000 / 2 - 1).U
val cntReg = RegInit(0.U(32.W))
val blkReg = RegInit(0.U(1.W))
cntReg := cntReg + 1.U
when(cntReg === CNT_MAX) {
cntReg := 0.U
blkReg := ~blkReg
}
io.led := blkReg
}

object Hello {
def main(args:Array[String]):Unit = {

(new ChiselStage).execute(
Array("--target", "verilog",
"--target-dir", "./rtl_out"),
Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new Hello()),
FirtoolOption("-disable-all-randomization"),
FirtoolOption("-strip-debug-info"),
FirtoolOption("--lowering-options=disallowPortDeclSharing"),
FirtoolOption("--default-layer-specialization=disable")
))

}
}

**What is the current behavior?**

when I use "class Hello extends Module{", it can generate the right verilog code wihtout init define.
but，when I use "class Hello extends Module with RequireAsyncReset { ", the verilog file still have register init define.

**What is the expected behavior?**
generate verilog file without reg init define.

**Please tell us about your environment:**

my build.sbt is >>>

ThisBuild / scalaVersion := "2.13.16"

lazy val root = (project in file("."))
.settings(
name := "untitled2"
)

scalaVersion := "2.13.16"
val chiselVersion = "7.11.0"
addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full)
libraryDependencies += "org.chipsalliance" %% "chisel" % chiselVersion

**Other Information**

**What is the use case for changing the behavior?**
use the line "class Hello extends Module with RequireAsyncReset {"

Start with the Scala reproducer in the issue and its build.sbt, comparing Hello with and without RequireAsyncReset. Run ChiselStage with FirtoolOption("-disable-all-randomization") and inspect the generated Verilog; done means the RequireAsyncReset version also has no register initialization definitions.

Written by the indexing model from the issue text.