Digital Top with Analog Black Box

I think I made a really poor assumption several months ago that I'm hoping someone with mixed signal design experience can clarify. If you have a digital top and you want to add in, say, an ADC black box, how would one go about doing that in Chisel? I assume you really just need to map the instance ports correctly, but in that case, is there still a notion of Width for AnalogType? And is inout really sufficient? Say you wanted to model your ADC with actual SystemVerilog and simulate via VCS. In that case, you'd have a 1-wide inout (or in) port that is of type "real", right? Anyways, my point is, fundamentally, AnalogType should not be of the same kind as UInt, SInt. If Analog is referring to in/out/inout behavior, it should be orthogonal to UInt, SInt, and ideally, Real. And I'm confused how the blackbox should be hooked up in Verilog.