suffix always be "sv"

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**
```
object Test extends App {
val firtoolOptions = Array(
"--verilog", // <=== **NO effect**
"--default-layer-specialization=enable",
"--verification-flavor=immediate",
"--strip-debug-info",
"--strip-fir-debug-info",
"--disable-all-randomization",
"--lowering-options=" + List(
"disallowLocalVariables",
"disallowPackedArrays",
"locationInfoStyle=wrapInAtSquareBracket"
).reduce(_ + "," + _)
)

val commonArgs = Array(
"--target", "verilog", // <=== **NO effect**
"--target-dir", "out/verilog",
"--split-verilog"
)

circt.stage.ChiselStage.emitSystemVerilogFile(new MyTest(), args ++ commonArgs, firtoolOptions)
}
```
**What is the current behavior?**
generating verilog named "MyTest.sv"

**What is the expected behavior?**
generating verilog named "MyTest.v", i.e. file extension name should be "v" when target is verilog, and be "sv" when target is systemverilog.

**Please tell us about your environment:**

WSL-ubuntu 24, chisel:7.7.0 , mill-0.12.11

**Other Information**

**What is the use case for changing the behavior?**

Start at circt.stage.ChiselStage.emitSystemVerilogFile and reproduce the reported invocation with --target verilog and --verilog. Trace how the target selects the generated filename extension, then verify that verilog output ends in .v while systemverilog output remains .sv.

Written by the indexing model from the issue text.