Escape FIRRTL Keywords in Emission

Change the emission of FIRRTL to escape all FIRRTL keywords by making them literal identifiers. E.g., if a port is called `UInt`, this should be emitted as `` `UInt` ``.

The following example should compile:

``` scala
//> using repository https://central.sonatype.com/repository/maven-snapshots
//> using scala 2.13.18
//> using dep org.chipsalliance::chisel:7.9.0
//> using plugin org.chipsalliance:::chisel-plugin:7.9.0
//> using options -unchecked -deprecation -language:reflectiveCalls -feature -Xcheckinit
//> using options -Xfatal-warnings -Ywarn-dead-code -Ywarn-unused -Ymacro-annotations

import chisel3._
import circt.stage.ChiselStage

class Foo extends RawModule {
val UInt = IO(chisel3.UInt(2.W))
UInt :<= 3.U
}

object Main extends App {
println(ChiselStage.emitCHIRRTL(new Foo))
println(
ChiselStage.emitSystemVerilog(
gen = new Foo,
args = Array("--throw-on-first-error", "--full-stacktrace", "--strip-debug-info")
)
)
}
```