chipsalliance / chipsalliance/chisel
[Scala3] SouceLine support for VerificationStatement API
- Dominant language
- Scala
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Description
**Type of issue**: Task
**Is your feature request related to a problem? Please describe.**
Scala 3 implementation of assert, assume and cover VerificationStatement APIs are missing support for detecting source lines. In Scala 2, this functionality is enabled by macros which grab the compile-time source line information.
**Describe the solution you'd like**
Source line-aware messages from verif APIs, either using Scala 3 macros or something else
**Describe alternatives you've considered**
"Missing source line" will be printed with these APIs until this is implemented
**Additional context**
Until this is implemented assert/assume/cover fires will note that source line information is unavailable with a link to this issue
**What is the use case for implementing this feature?**
Keep the behavior in Scala 3 same as in Scala 2
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Assessment
This issue has not been assessed yet.