Allow zero length VecInit()

**Type of issue**: Feature Request

Allow zero length VecInit()

**Is your feature request related to a problem? Please describe.**

If I try to create a zero length VecInit(), I get "Vec hardware values are not allowed to be empty"

**Describe the solution you'd like**

Allow zero length VecInit()

**Describe alternatives you've considered**

Iffy code in modelling.

**Additional context**

**What is the use case for implementing this feature?**

## Use Case: Zero-Length `VecInit()` in Chisel Modeling and Testbenches

Chisel’s power as a hardware DSL extends beyond synthesizable RTL—it enables expressive, parameterized modeling and testbenches.

An example is the use of **zero-length `VecInit()`**:

- **Zero-length Vecs are not hardware** (no wires or registers are emitted), but are useful for parameterized designs.
- They allow you to write generic code that naturally handles edge cases (like zero ports, lanes, or slices) without special-case logic or errors.
- This is especially valuable in **non-synthesizable modeling and testbenches**, where parameter sweeps and corner cases (including zero) are common.
- Even in RTL, zero-length Vecs can simplify parameterized code, letting cases reduce to zero cleanly for some configurations.

**Chisel lets you:**
- Write one unified, hardware-like model for both RTL and testbenches.
- Use constructs like `VecInit()` with zero length for flexible, robust parameterization.
- Avoid hacks, special cases, or non-hardware workarounds found in other HDLs.

**Bottom line:**
Chisel’s support for zero-length `VecInit()` is a practical example of how its modeling capabilities go beyond RTL, making it easier to write, test, and verify highly parameterized hardware

> Chisel solves the underlying problem that made Verilog so hard to use for modeling and testbenches—a problem that led to a patchwork of workarounds like SystemC, cocotb, DPI/FFI hacks, and custom event loops.
> Instead of relying on these ad-hoc paradigms, Chisel lets you express parallelism and hardware behavior directly and naturally, all within a unified, hardware-centric DSL.
> By writing everything in Chisel, you get clearer, more maintainable, and more accurate models and testbenches—without the complexity and fragmentation of mixing

## Loosely-Timed Models with DecoupledIO

Chisel makes it easy to build loosely-timed models directly in the hardware DSL using `DecoupledIO`.
By leveraging `DecoupledIO` and its built-in ready/valid handshake, you can naturally express transaction-level interfaces, backpressure, and flow control.
This allows you to model systems where timing between transactions is flexible, without needing to manually manage threads or coroutines—enabling high-level, protocol-faithful modeling that remains hardware-consistent and easy to manually manage threads or coroutines—enabling high-level, protocol-faithful modeling that remains hardware-consistent and easy to reason about.