chipsalliance / chipsalliance/chisel

Chisel asserts should give file and line number to Chisel as well as systemverilog

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Scala
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Description

**Type of issue**: Feature Request

```
chisel3.simulator.Exceptions$AssertionFailed: One or more assertions failed during Chiselsim simulation
------------------------------------------------------------------------------
The following assertion failures were extracted from the log file:

lineNo line
----------------------------------------------------------------------------
0 [21] %Error: XxxTestBench_Verification_Assert.sv:301: Assertion failed in TOP.svsimTestbench.dut.verification_assert.unnamedblk1: Assertion failed: Must be positive

For more information, see the complete log file:

test_run_dir/aptos.Simulator_889627/workdir-default/simulation-log.txt
```

**Is your feature request related to a problem? Please describe.**

I have to dig into the XxxTestBench_Verification_Assert.sv file to find the Chisel .scala file and line number

**Describe the solution you'd like**

Print out the .scala filename and line number of the assert

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