chipsalliance / chipsalliance/chisel
ImportedDefinitionExtModule does not include secret ports (bores)
- Dominant language
- Scala
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Description
**Type of issue**: Bug Report
**Please provide the steps to reproduce the problem:**
**What is the current behavior?**
If I have a module which has bored (secret) ports, and I create an ImportedDefinitionExtModule from it, those ports are not included in the extmodule
**What is the expected behavior?**
Those bored ports should be included in the extmodule .fir. Note that since it might be hard to actually *drive* them since they can't really be marked @public, this might just mean you get firrtl error about invalid / undriven ports.
**Please tell us about your environment:**
**Other Information**
**What is the use case for changing the behavior?**
Should realize before .sv simulation time that some ports are undriven
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Assessment
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