Inaccrate Infomation in the "Get me Verilog" section of FAQ

In the "Get me Verilog" section of the FAQ page (the links below), some information might be ambiguous, inaccurate, or outdated.

https://github.com/chipsalliance/chisel/blob/main/docs/src/resources/faqs.md#get-me-verilog

https://www.chisel-lang.org/docs/resources/faqs#get-me-verilog

The FAQ says that the following code generates a `HelloWorld.v` under PWD. However, `emitSystemVerilog` returns a string, and it is `emitSystemVerilogFile` that generates a file.

```scala
import circt.stage.ChiselStage
object VerilogMain extends App {
ChiselStage.emitSystemVerilog(new HelloWorld)
}
```

The FAQ also suggests running the following command for fine control over verilog generation.

```sh
sbt 'runMain intro.HelloWorld --target-dir buildstuff --top-name HelloWorld'
```

However, the code spinet in the page does not contain an `intro.HelloWorld` object extending `App`, so this command will fail. Some code like this is needed for the above command to work.

```scala
object HelloWorld extends App {
ChiselStage.emitSystemVerilogFile(new HelloWorld, args)
}
```

Start in docs/src/resources/faqs.md at the “Get me Verilog” section and compare the prose and examples with the emitSystemVerilog and emitSystemVerilogFile behavior described in the issue. Check the sbt command against the shown Scala snippet, then update the FAQ so the file-generation API and required entry point are accurate.

Written by the indexing model from the issue text.