ChiselSim not allowing capturing of stdout/stderr

ChiselSim should allow for capturing stdout.

I'm not sure what is going on here, but something with ChiselSim and svsim is preventing capturing stdout. See the following:

``` scala
//> using scala "2.13.16"
//> using repository sonatype-s01:snapshots
//> using dep "org.chipsalliance::chisel::7.0.0-M2+599-7965f8e4-SNAPSHOT"
//> using plugin "org.chipsalliance:::chisel-plugin::7.0.0-M2+599-7965f8e4-SNAPSHOT"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.util.Counter
import chisel3.simulator.ChiselSim
import chisel3.simulator.stimulus.RunUntilFinished
import java.io.{File, FileOutputStream}

class Foo extends Module {

val (count, done) = Counter(true.B, 8)

printf("%d\n", count)

when (done) {
stop()
}

}

object Main extends App with ChiselSim {

val out = new FileOutputStream(new File("out.log"))
val err = new FileOutputStream(new File("err.log"))
Console.withOut(out) {
Console.withErr(err) {
simulate(new Foo)(RunUntilFinished(10))
println("hello out")
System.err.println("hello err")
}
}

}
```

Running this shows:

```
# scala-cli Foo.scala
Compiling project (Scala 2.13.16, JVM (22))
Compiled project (Scala 2.13.16, JVM (22))
0
1
2
3
4
5
6
7
hello err
```

File contents are then:

```
# cat err.log
# cat out.log
hello out
```

Standard out and standard err should so something predictable here.

Start at ChiselSim.simulate and its svsim integration, using the provided Console.withOut and Console.withErr example to trace where simulator output is written. Compare stdout and stderr handling during simulation with the surrounding Scala println calls. Done means standard output and standard error are captured predictably in the respective files.

Written by the indexing model from the issue text.