AddDedupGroupAnnotations creates invalid Annotations w/ Definition argument

Consider the following:

``` scala
//> using repository "sonatype-s01:snapshots"
//> using scala "2.13.15"
//> using dep "org.chipsalliance::chisel:7.0.0-M2+432-486b55dc-SNAPSHOT"
//> using plugin "org.chipsalliance:::chisel-plugin:7.0.0-M2+432-486b55dc-SNAPSHOT"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.stage.ChiselGeneratorAnnotation
import chisel3.experimental.hierarchy.{
Definition,
Instance,
instantiable,
public
}
import circt.stage.ChiselStage

@instantiable
class AddOne(val width: Int) extends Module {
@public val width = width
@public val in = IO(Input(UInt(width.W)))
@public val out = IO(Output(UInt(width.W)))
out := in + 1.U
}

class AddTwo(addOneDef: Definition[AddOne]) extends Module {
val i0 = Instance(addOneDef)
val i1 = Instance(addOneDef)
val in = IO(Input(UInt(addOneDef.width.W)))
val out = IO(Output(UInt(addOneDef.width.W)))
i0.in := in
i1.in := i0.out
out := i1.out
}

object Main extends App {
private val gen = () => new AddTwo(Definition(new AddOne(10)))

new ChiselStage()
.execute(
args = Array("--target", "systemverilog"),
annotations = Seq(ChiselGeneratorAnnotation(gen))
)
}
```

This creates illegal annotations in the circuit due to the dedup group phase. Specifically, this creates annotations that have the definition as the circuit when this is illegal:

```
~AddOne|AddOne
```

This should be:

```
~AddTwo|AddOne
```