Weird paths/Targets for Module Choices

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**

Run the following code on 6.6.0 or head of main.

```scala
import chisel3._
import chisel3.experimental.{annotate, BaseModule}
import chisel3.properties.{Path, Property}
import firrtl.annotations.{ReferenceTarget, SingleTargetAnnotation}
import chisel3.choice.{Case, Group, ModuleChoice}
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage

class MyIO(width: Int) extends Bundle {
val in = Flipped(UInt(width.W))
val out = UInt(width.W)
val prop1 = Output(Property[Path]())
val prop2 = Output(Property[Path]())
}
object MyChoice extends Group {
object FooBar extends Case
}
class DefaultTarget(parent: BaseModule) extends FixedIORawModule[MyIO](new MyIO(8)) {
io.out := io.in
io.prop1 := Property(Path(io.out))
io.prop2 := Property(Path(io.out.toRelativeTarget(Some(parent))))
}
class FooBarTarget(parent: BaseModule) extends FixedIORawModule[MyIO](new MyIO(8)) {
io.out := io.in
io.prop1 := Property(Path(io.out))
io.prop2 := Property(Path(io.out.toRelativeTarget(Some(parent))))
}

class Top extends Module {
val inst = ModuleChoice(new DefaultTarget(this))(Seq(MyChoice.FooBar -> new FooBarTarget(this)))
inst.suggestName("potato") // Show that ModuleChoices are reactive to naming of the Data
}

object Top extends App {
println(
ChiselStage.emitCHIRRTL(
gen = new Top,
)
)
}
```

**What is the current behavior?**

The paths are as follows:
```firrtl
module DefaultTarget :
...
propassign prop1, path("OMReferenceTarget:~Top|DefaultTarget>out")
propassign prop2, path("OMReferenceTarget:~Top|Top/inst_instDefaultModule:DefaultTarget>out")

module FooBarTarget :
...
propassign prop1, path("OMReferenceTarget:~Top|FooBarTarget>out")
propassign prop2, path("OMReferenceTarget:~Top|Top/potato:FooBarTarget>out")
```

**What is the expected behavior?**

The paths should use the right name:
```firrtl
module DefaultTarget :
...
propassign prop1, path("OMReferenceTarget:~Top|DefaultTarget>out")
propassign prop2, path("OMReferenceTarget:~Top|Top/potato:DefaultTarget>out")

module FooBarTarget :
...
propassign prop1, path("OMReferenceTarget:~Top|FooBarTarget>out")
propassign prop2, path("OMReferenceTarget:~Top|Top/inst_choiceModules_0_2:FooBarTarget>out")
```

**Please tell us about your environment:**

**Other Information**

**What is the use case for changing the behavior?**

It's unclear what getting paths like this across specific Module choices should mean in firrtl or if it's really the right way to do this. Regardless, Chisel should do the sensible thing instead of whatever it's currently doing.

Start by running the supplied Scala reproducer with ChiselStage.emitCHIRRTL on 6.6.0 or main, then compare the generated paths for DefaultTarget and FooBarTarget with the expected output. Trace ModuleChoice, suggestName, and toRelativeTarget behavior to establish the intended path semantics; done means the paths use the appropriate names consistently.

Written by the indexing model from the issue text.